1. Field of the Invention
The present invention relates generally to communication systems and, more particularly, to a simplified system of detecting and reducing errors in processing binary frequency shift keyed signals.
2. Description of the Prior Art
Many communication systems use digital modulation techniques in signal transmission. One such digital transmission technique involves frequency shift keyed (FSK) modulation. Frequency shift keying involves the modulation of a base or carrier frequency to shift its frequency by predetermined increments in response to particular data to be transmitted.
In a frequency modulated (FM) system, the frequency shift phase is continuous, i.e. the transmitted signal is a sinusoidal signal which varies in frequency but has no time phase shift continuity. In a binary FSK system normally, a binary "1" or "mark" signal is transmitted at a frequency above a selected center frequency and is known as a "carrier plus" frequency. A binary "0" or "space" is transmitted at a frequency below the center frequency of the carrier or a "carrier minus" frequency.
Systems for producing frequency shift keyed transmission signals are well known. In such systems, the differential between the transmitted frequency and the center frequency of the carrier is normally made equal to or slightly greater than the modulation rate required, or data rate required, divided by two. Because these signals are normally fairly close together in frequency and because spurious signals or noise signals are usually received from time to time, it is necessary for any receiving unit to accurately discriminate between the mark and space frequencies and between either of these and other noise signals so that proper discrimination in reception and use of the signal can be made.
In the prior art many schemes have been suggested in an attempt to assure that correct identification of mark and space signals occur in binary FSK receiver systems. One such prior art receiver system is illustrated and described in U.S. Pat. No. 3,348,153, issued Oct. 17, 1967. That patent illustrates and describes a system which uses a binary logic scheme which assumes the reception of a binary "1" or mark signal if either of two events occur. One such event is the detection of the presence of a mark signal and the other is the detection of the complement or absence of a space signal. Conversely, the detection of the presence of a space signal or the detection of the complement of a mark signal will be taken as a space signal. After the signals have traversed other gates, the determination is finally made by two OR gates which feed signals to a flip-flop or output device which changes state accordingly. Compensation is made for the presence or absence of both signals simultaneously such that the flip-flop is not triggered. The flip-flop or output device, thus, may be triggered although the necessary FSK system frequency may be entirely missing in the reference input signal.